Lead frame with plated end leads

ABSTRACT

A lead frame comprising a frame which defines a central opening. Disposed within the central opening is a die pad which is connected to the frame. Also connected to the frame are a plurality of leads which extend within the opening toward the die pad. Each of the leads defines opposed top and bottom surfaces, an inner end, an outer end, and an opposed pair of side surfaces. The bottom surface and the outer end collectively define a corner region of the lead. Formed within the corner region is a recess which is sized and configured to accommodate the flow of reflow solder thereinto.

RELATED APPLICATIONS

The present application is a continuation of U.S. application Ser. No.10/122,598 entitled LEAD FRAME WITH PLATED END LEADS AND RECESSES filedApr. 15, 2002 now U.S. Pat. No. 6,608,366.

STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT

(Not Applicable)

BACKGROUND OF THE INVENTION

The present invention relates generally to integrated circuit chippackage technology, and more particularly to a unique lead frame designfor a micro lead frame (MLF) package wherein a special platedhalf-etched feature is included in the lead frame design which increasesthe solderable area of the leads of the lead frame to a printed circuitboard, thus creating stronger final solder joints with increased secondlevel reliability.

Integrated circuit dies are conventionally enclosed in plastic packagesthat provide protection from hostile environments and enable electricalinterconnection between the integrated circuit die and an underlyingsubstrate such as a printed circuit board (PCB) or motherboard. Theelements of such a package include a metal lead frame, an integratedcircuit die, bonding material to attach the integrated circuit die tothe lead frame, bond wires which electrically connect pads on theintegrated circuit die to individual leads of the lead frame, and a hardplastic encapsulant material which covers the other components and formsthe exterior of the package.

The lead frame is the central supporting structure of such a package. Aportion of the lead frame is internal to the package, i.e., completelysurrounded by the plastic encapsulant. Portions of the leads of the leadframe extend externally from the package or are partially exposed withinthe encapsulant material for use in electrically connecting the chippackage to another component. In certain chip packages, a portion of thedie pad of the lead frame also remains exposed within the exterior ofthe package for use as a heat sink.

For purposes of high-volume, low-cost production of chip packages, acurrent industry practice is to etch or stamp a thin sheet of metalmaterial to form a panel or strip which defines multiple lead frames. Asingle strip may be formed to include multiple arrays, with each sucharray including a multiplicity of lead frames in a particular pattern.In a typical chip package manufacturing process, the integrated circuitdies are mounted and wire bonded to respective ones of the lead frames,with the encapsulant material then being applied to the strip so as toencapsulate the integrated circuit dies, bond wires, and portions ofeach of the lead frames in the above-described manner.

Upon the hardening of the encapsulant material, the lead frames withinthe strip are cut apart or singulated for purposes of producing theindividual chip packages. Such singulation is typically accomplished viaa saw singulation process. In this process, a saw blade is advancedalong “saw streets” which extend in prescribed patterns between the leadframes as required to facilitate the separation of the lead frames fromeach other in the required manner.

As indicated above, in certain current MLF package designs, the bottomsurface of each of the leads of the lead frame is exposed within thebottom surface of the package body formed by the hardening of theencapsulant material, with one end surface of each of the leads beingexposed within a corresponding peripheral or side surface of the packagebody. In this design, solderable surfaces are provided on only thebottom surface of the package body, and more particularly, by theexposed bottom surfaces of the leads. The MLF package is attached to theprinted circuit board or motherboard by printing solder paste on theboard, positioning the exposed bottom surfaces of the leads upon thesolder paste, and completing a hot reflow process. However, the limitedsolderable area on the MLF package and resultant decreased solder jointstrength gives rise to reliability problems concerning the potentialfailure of one or more of the solder joints between the MLF package andthe motherboard. Previous attempts to increase solder joint life were tooptimize or increase the size of the leads, the material set, and theboard design. However, material sets which give the best package levelperformance may also produce the worst board level performance, thusnecessitating another option to increase overall solder strength andreliability between the MLF package and the motherboard.

The present invention addresses the solder joint reliability issue byproviding a lead frame design wherein those surfaces of the leadsexposed within the bottom and side surfaces of the package body areplated and configured in a manner allowing solder to reflow up the leadends, thereby increasing the overall solder joint strength andreliability between the MLF package and motherboard. In this regard, theplated lead ends increase the solderable area of the leads of the MLFpackage to the motherboard, with the final solder joint being strongerwith increased second level reliability.

The uniquely configured lead ends may be formed as a half-etched featurein the lead frame design. This half-etched design has the effect ofincreasing saw efficiency in the saw singulation process due to theresultant reduction of copper or other metal in the saw streets. Thehalf-etched design further reduces the cut line interface between thesaw and each of the leads, thus reducing the amount of burring whichtypically occurs upon the leads as a result of the saw singulationprocess. Saw generated burrs at the seating plan of each lead in thelead frame adversely affect solder mounting and joint reliability. Incurrent MLF package fabrication methodologies, lead burrs are controlledby limiting the feed rate of the saw along the saw streets and by usingspecifically developed, high cost saw blades. The reduced burringattributable to the half-etched design of the lead ends increases outputand allows for the use of lower cost saw blades.

As indicated above, as a result of forming the half-etched plated endsof the leads, metal material is removed from the saw streets, thusreducing the area of each of the leads susceptible to burring. Thisplated, half-etched feature in the present lead frame design becomes anintegral part of the finished lead connection of the MLF package. Theuniquely configured, plated ends of the leads of the lead frameconstructed in accordance in accordance with the present invention mayalternatively be formed through the implementation of a two-pass sawprocess, though such process does not provide the same saw cutefficiency and reduced burring attributes of the half-etched design. Thehalf-etched or sawed leads can be incorporated into standard lead framedesigns at no additional cost, and provide higher board-level (solderjoint) reliability and improved lead dimensional stability. In the caseof the half-etched leads, further advantages include the improvement ofthe saw singulation process (increased saw cut efficiency), and reducedburring on the saw cut leads as indicated above.

BRIEF SUMMARY OF THE INVENTION

In accordance with the present invention, there is provided a lead framewhich comprises a frame defining a central opening. Disposed within thecentral opening is a die pad which is connected to the frame. Alsoconnected to the frame are a plurality of leads which extend within theopening toward the die pad. Each of the leads defines opposed top andbottom surfaces, an inner end, an outer end, and an opposed pair of sidesurfaces. The bottom surface and the outer end collectively define acorner region of the lead. Formed within the corner region is a recess.The recesses facilitate the reflow of solder up the lead ends, therebyincreasing the overall solder joint strength and reliability between thesemiconductor package incorporating the lead frame and an underlyingsubstrate such as a printed circuit board or motherboard. The surfacesof the lead defining the recess are plated, with the inclusion of therecess within each lead effectively increasing the solderable area ofthe leads of the semiconductor package to the printed circuit board,with the final solder joint being stronger with increased second levelreliability.

The recesses within the leads may be formed as a half-etched feature inthe lead frame design. This half-etched design has the effect ofincreasing saw efficiency in the saw singulation process due to theresultant reduction of copper or other metal material in the sawstreets. The half-etched design further reduces the cut line interfacebetween the saw and each of the leads, thus reducing the amount ofburring which typically occurs upon the leads as a result of the sawsingulation process.

Further in accordance with the present invention, there is provided amodified inboard design for a semiconductor package which is adapted tofacilitate an increase in second level solder joint reliability bycreating solder fillets upon those portions of the bottom surfaces ofthe leads which are exposed within the bottom surface of the packagebody. More particularly, the solder fillets are created by formingcopper bumps upon the exposed bottom surfaces of each of the leads, thecopper bumps facilitating the creation of solder fillets. Each of thecopper bumps may optionally include a solder plate formed thereon.

The present invention is best understood by reference to the followingdetailed description when read in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

These, as well as other features of the present invention, will becomemore apparent upon reference to the drawings wherein:

FIG. 1 is a partial top plan view of a lead frame strip definingmultiple lead frames formed in accordance with a first embodiment of thepresent invention;

FIG. 2 is a cross-sectional view taken along line A—A of FIG. 1;

FIG. 3 is a cross-sectional view taken along line B—B of FIG. 1;

FIG. 4 is a partial top plan view of the lead frame strip shown in FIG.1 as modified to improve the efficiency of a saw singulation processused to separate the individual lead frames within the lead frame stripfrom each other;

FIG. 5 is a cross-sectional view taken along line A—A of FIG. 4;

FIG. 6 is a cross-sectional view taken along line a—a of FIG. 4;

FIG. 7 is a top perspective view of a semiconductor package formed toinclude the lead frame of the first embodiment of the present invention;

FIG. 8 is a bottom plan view of the semiconductor package shown in FIG.7;

FIG. 9 is a partial perspective view of the encircled region A shown inFIG. 8;

FIG. 10 is an enlargement of the encircled region B shown in FIG. 9;

FIG. 11 is a partial, side-elevational view illustrating the manner inwhich the semiconductor package shown in FIGS. 7–10 is mounted to aprinted circuit board;

FIG. 12 is a partial top plan view of a lead frame strip definingmultiple lead frames formed in accordance with a second embodiment ofthe present invention;

FIG. 13 is a cross-sectional view taken along line A—A of FIG. 12;

FIGS. 14A, 14B, 14C are cross-sectional views taken along line B—B ofFIG. 12, illustrating a sequence of saw cutting steps through which thelead frame of the second embodiment is formed;

FIG. 15 is a cross-sectional view of a semiconductor package having amodified in-board design to define solder fillets created by copperbumps in accordance with another aspect of the present invention;

FIGS. 16A–16F are cross-sectional views illustrating a sequence of stepswhich may be used to fabricate the semiconductor package shown in FIG.15.

Common reference numerals are used throughout the drawings and detaileddescription to indicate like elements.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawings wherein the showings are for purposes ofillustrating preferred embodiments of the present invention only, andnot for purposes of limiting the same, FIG. 1 depicts a lead frame strip10 which is uniquely configured to facilitate the production of amultiplicity of lead frames 12 which are each formed in accordance withthe present invention. The strip 10 has a generally rectangularconfiguration, defining opposed pairs of longitudinal and lateralperipheral edge segments. The strip 10 is typically formed to definemultiple, identically configured arrays, with a portion of one sucharray being shown in FIG. 1. Each array defines a multiplicity of thelead frames 12.

Each lead frame 12 comprises an outer frame portion 14 which defines acentrally positioned opening 16. Disposed within the opening 16 is a diepad 18 of the lead frame 12. Though not shown in FIG. 1, the die pad 18is typically connected to the outer frame portion 14 by a plurality oftie bars 15 of the lead frame 12 which extend between the outer frameportion 14 and respective ones of the four corner regions typicallydefined by the die pad 18. The tie bars 15 facilitate the stable supportof the die pad 18 inside the outer frame portion 14, and moreparticularly within the opening 16 defined thereby.

Each lead frame 12 further comprises a multiplicity of leads 20 whichare integrally connected to the outer frame portion 14 and protrudetherefrom into the opening 16 toward the peripheral edge of the die pad18. The leads 28 are typically segregated into four equal sets, witheach set being disposed in spaced relation to a respective one of thefour peripheral edge segments defined by the die pad 18. Each lead 20defines a distal, inner end 22 which, as indicated above, is disposed inspaced relation to the peripheral edge of the corresponding die pad 18.As further seen in FIG. 1, each lead 20 has a generally rectangularconfiguration, and defines an opposed pair of longitudinal side surfaces24. The inner end 22 extends perpendicularly between the side surfaces24, and itself defines a lateral side surface of the lead 20. Each lead20 further defines a top surface 26 (shown in FIGS. 2 and 3) and anopposed bottom surface 28. The bottom surfaces 28 of the leads 20 areshown in FIG. 1.

In each array within the strip 10, the outer frame portions 14 of thelead frames 12 are integrally connected to each other such that the leadframes 12 of each array are arranged in a matrix wherein the leads 20thereof extend in multiple rows and columns. As further seen in FIG. 1,each set of leads 20 within each column and row extends in opposed,spaced relation to a set of leads 20 of an adjacent lead frame 12 withinthe same column or row, with the adjacent sets of leads 20 beingseparated from each other by a gap G collectively defined by portions ofthe corresponding, integrally connected outer frame portions 14 of thelead frames 12. Formed in each gap G of the strip 10 are a plurality ofelongate slots 30. Each slot 30 extends across the corresponding gap Gbetween a respective opposed pair of leads 20. Each slot 30 is sizedsuch that the opposed ends thereof extend or protrude into each of theleads 20 of the corresponding pair for reasons which will be discussedin more detail below.

The strip 10 typically comprises a first layer which is formed from aninsulating material (e.g., a molding compound), and a second layer whichis applied to the first layer and formed from a conductive metallicmaterial (e.g., copper). The second layer defines the lead frames 12 andslots 30. The second layer of the strip 10 is preferably formed bychemical etching, with the slots 30 being formed through theimplementation of a half-etched technique. In this regard, wherein thefirst layer is exposed within the opening 16, the slots 30 do not extendall the way to the first layer.

In the strip 10, each gap G (collectively defined by sections of theouter frame portions 14 as indicated above), portions of the leads 20extending thereto, and the slots 30 formed therein collectively define asaw street S of the strip 10. Due to the arrangement of the lead frames12 in a matrix within each array of the strip 10, multiple lateral andlongitudinal saw streets S are defined within the strip 10. In themanufacture of integrated circuit chip packages from the strip 10, thepassage of a cutting blade along each saw street S separates the leadframes 12 from each other. During the saw singulation process used toseparate the lead frames 12 from each other, the saw blade cutting alongeach saw street S removes the metal material collectively defined by theouter frame portions 14 in each gap G, and further removes or severs aportion of each lead 20 disposed furthest from the corresponding die pad18. Additionally, the saw blade passes through each slot 30 within eachgap G. As it cuts along each saw street S, the saw blade is alwayscutting the metal within the gap G, though the amount of metal cut isreduced when the saw blade passes through the aligned spaces separatingthe leads 20 from each other (such spaces including only the first layerdue to the complete etching of the metal second layer) and the slots 30(attributable to the reduced thickness facilitated by the half-etchedsecond layer).

Referring now to FIGS. 2, 3 and 10, the completion of the sawsingulation process results in each lead 20 of each separated lead frame12 being formed to include an outer end 32 which is disposed in opposedrelation to the corresponding inner end 26 and defines another lateralside surface of the lead 20. As indicated above, the opposed ends ofeach slot 30 are formed within the strip 10 so as to extend into theleads 20 of each opposed pair extending to the corresponding gap G. Thewidth of the saw blade used in the saw singulation process is such thateach saw street S does not include the opposed end portions of each slot30. Thus, as best seen in FIGS. 2, 3, 9 and 10, the completion of thesaw singulation process results in a recess 34 being formed within eachlead 20. Each recess 34 is formed in a corner region of thecorresponding lead 20 collectively defined by the outer end 32 andbottom surface 28 thereof. In this regard, the recess 34 is disposedwithin the bottom surface 28 and outer end 32, but does not extend tothe top surface 26 or either of the side surfaces 24. Additionally, theinnermost end of each recess 34 is disposed in spaced relation to theinner end 22 of the corresponding lead 20. The use of the recesses 34will be discussed in more detail below.

Referring now to FIGS. 4–6, it is contemplated that to further improvesawing efficiency in the saw singulation process, the strip 10 mayfurther be formed to include a plurality of secondary slots 36 whichextend in alignment within each gap G. More particularly, as best seenin FIG. 4, each secondary slot 36 extends along an axis bisecting thecorresponding gap G. Thus, each secondary slot 36 extendsperpendicularly relative to the slots 30, with certain ones of thesecondary slots 36 extending between adjacent pairs of the slots 30. Thesecondary slots 36 may also be formed via a half-etched technique withinthe second layer of the strip 10 in the same manner the slots 30 areformed therein. Alternatively, the secondary slots 36 may be formed bycompletely etching the second layer, thus causing the first layer to beexposed within the secondary slots 36. Irrespective of whether they areformed by a half-etched technique or completely etching the second layerof the strip 10, the inclusion of the secondary slots 36 within thestrip 10 further reduces the amount of metal material within each sawstreet S which must be removed by the saw blade during the sawsingulation process. Such reduced amount of metal material within thesaw street S increases sawing efficiency and prolongs saw blade life,thus reducing premature blade wear and providing a substantial costbenefit.

In addition to the slots 30 (alone or in combination with the secondaryslots 36) increasing saw efficiency in the saw singulation process dueto the resultant reduction of copper or other metal material in each sawstreet S, the slots 30 further reduce the cut line interface between thesaw blade and each of the leads 20, thus reducing the amount of burringwhich typically occurs as a result of the saw singulation process. Asindicated above, saw generated burrs at the seating plan of each lead 20in the lead frame 12 adversely affect solder mounting and jointreliability. In current semiconductor package fabrication methodologies,lead burrs are controlled by limiting the feed rate of the saw bladealong each saw street S and by using specifically developed, high costsaw blades. The reduced burring attributable to the inclusion of theslots 30 within the strip 10 increases output and allows for the use oflower cost saw blades, thereby providing a further increased costbenefit. Stated another way, the reduced area of those portions of eachof the leads 20 which are cut by the saw blade during the sawsingulation process attributable to the removal of metal material by theformation of the slots 30 in turn reduces the area of the leads 20susceptible to burring.

Referring now to FIGS. 7–10, there is depicted a semiconductor package40 fabricated to include the lead frame 12 of the present invention. Thesemiconductor package 40 includes a package body 42 which is formed bythe hardening of the plastic encapsulant material which is applied tothe lead frame strip 10. As will be recognized, the saw singulationprocess which effectively separates the lead frames 12 of the strip 10from each other also facilitates the cutting of the plastic encapsulantmaterial in a manner completing the formation of the package body 42 ofeach semiconductor package 40. The completely formed package body 42defines a top surface 44 and an opposed bottom surface 46. The packagebody 42 further defines a generally planar shelf or shoulder 48 which isperpendicularly recessed relative to the top surface 44 and extends ingenerally parallel relation thereto. Extending perpendicularly betweenthe shoulder 48 and the bottom surface 46 is a peripheral side surface50 of the package body 42.

The package body 42 of the semiconductor package 40 is applied to thelead frame 12 such that the bottom surface of the die pad 18 is exposedwithin the bottom surface 46 of the package body 42. Additionally, atleast portions of the bottom surfaces 28 of the leads 20 of the leadframe 12 are exposed within the bottom surface 46 of the package body42, with the outer ends 32 of the leads 20 being exposed within the sidesurface 50 of the package body 42. Thus, each of the recesses 34 isfully exposed within the semiconductor package 40. The inner ends 22,side surfaces 24 and top surfaces 26 of the leads 20 are covered by thepackage body 42, as are the top and side surfaces of the die pad 18. Asshown in FIGS. 7 and 8, the package body 42 may be formed such that thebottom surfaces of the above-described tie bars 15 used to connect thedie pad 18 to the outer frame portion 14 are exposed within respectiveones of the four corner regions of the bottom surface 46 of the packagebody 42. The outer ends of the tie bars may be exposed within the sidesurface 50 of the package body 42, with the inner ends, top surfaces andside surfaces of the tie bars 15 being covered by the package body 42.In the semiconductor package 40, the bottom surface 28 and outer end 32of each lead 20 (which are exposed within the package body 42)preferably include a plating layer of a predetermined thickness platedthereon. Such plating layer is typically a metal such as copper, gold,solder, tin, nickel, palladium, or others. The plating layer will alsocoat or be applied to those surfaces of each lead 20 defining the recess34 therein.

Referring now to FIG. 11, as indicated above, in current chip packagedesigns, solderable surfaces used to facilitate the electricalconnection of the chip package to a printed circuit board are providedby only the exposed bottom surfaces of the leads. The chip package isattached to the printed circuit board by printing solder paste on theboard, positioning the exposed bottom surfaces of the leads upon thesolder paste, and completing a hot reflow process. However, the limitedsolderable area of the chip package and resultant decreased solder jointstrength gives rise to reliability problems concerning the potentialfailure of one or more of the solder joints between the chip package andthe printed circuit board. The inclusion of the recesses 34 in the leads20 within the semiconductor package 40 allows solder to reflow up theouter ends 32 of the leads 20 (within the recesses 34) during the hotreflow process, thereby increasing the overall solder joint strength andreliability between the semiconductor package 40 and the printed circuitboard 52 as shown in FIG. 11. The inclusion of the recesses 34 withinthe leads 20 increases the solderable area of the leads 20 to theprinted circuit board 52, with the final solder joint being strongerwith increased second level reliability.

Referring now to FIGS. 12–14C, in accordance with a second embodiment ofthe present invention, it is contemplated that the leads 20 may beformed to include alternatively configured recesses 54 within the cornerregion of each lead 20 collectively defined by the outer end 32 andbottom surface 28 thereof. The alternatively configured recesses 54 areformed via a sequence of saw cuts. In this regard, the strip 10 used toform the lead frames 12 having the leads 20 which include the recesses54 does not include the slots 30 or the secondary slots 36 discussedabove. As seen in FIGS. 12 and 14A, the recesses 54 are formed by thecompletion of a first saw cut S1 wherein the saw blade cuts into thebottom surfaces 28 of those portions of the leads 20 of adjacent leadframes 12 extending to a common gap G. As seen in FIG. 14A, the metalremoved by this first saw cut amounts to approximately half the totalthickness of the leads 20. Subsequent to the completion of the first sawcut, the bottom surfaces 28 of the leads 20 are plated, as are thosesurfaces of each lead 20 formed or defined by the first saw cut S1.

As seen in FIGS. 12 and 14C, upon the completion of the plating process,a second saw cut S2 is completed through the use of a saw blade which isthinner than that used to complete the first saw cut S1. The second sawcut S2 cuts through the entire strip 10, thereby effectively separatingthe lead frames 12 from each other. The second saw cut S2 furthercompletely removes portions of each of the leads 20 in a mannerfacilitating the formation of the outer ends 32 thereof and the recesses54 within the outer ends 32 and bottom surfaces 28. Each recess 54 has agenerally rectangular configuration and extends to each of the sidesurfaces 24.

The recesses 54 formed in accordance with the second embodiment of thepresent invention provide the same functionality as the recesses 34,i.e., allow solder to reflow up the ends of the leads 20 within therecesses 54. However, the formation of the recesses 54 via the two-passsaw process does not provide the same saw cut efficiency and reducedburring attributes as result from the formation of the recesses 34through the use of the slots 30.

Further in accordance with the present invention, it is contemplatedthat the leads 20 of each of the lead frames 12 may have a solder bump56 formed thereon prior to any saw singulation of the strip 10 eitheralong the saw street S or first and second saw cuts S1, S2. Exemplarysolder bumps 56 formed on one of the leads 20 are shown in FIGS. 1 and12. If the solder bumps 56 are to be pre-formed on each of the leads 20including the recesses 34, the singulation of the strip 10 to separatethe lead frames 12 from each other and thus complete the fabrication ofthe semiconductor packages will occur in a two-step process. In thefirst step, an “iso cut” will be completed along the saw street S. As aresult of this initial cut, the conductive metal material (e.g., copper)of the second layer is removed along the saw street S, with theinsulating material of the first layer being left intact. Upon thecompletion of the iso cut, the solder bumps 56 are applied to the leads20 of each of the lead frames 12. Thereafter, a second cut is completedalong the saw street S by a saw blade which is thinner than the sawblade used to complete the iso cut. In the second, follow-up sawingprocess, the saw blade cuts only through the first layer due to theremoval of the second layer as a result of the iso cut. The use of athinner blade for completing the second cut prevents any burring orsmearing of the solder bumps 56 which could extend to the saw street S.The completion of the second cut completes the saw singulation of thestrip 10 and completes separation of the lead frames 12 from each other.

If the solder bumps 56 are to be pre-formed on each of the leads 20including the recesses 54, the complete fabrication of the semiconductorpackages will occur in a three-step process. The first step would entailthe completion of the first saw cut S1 described above in relation toFIG. 14A. Thereafter, the second saw cut S2 previously described inrelation to FIG. 14C would be completed. However, the second saw cut S2would be completed in a manner wherein only the conductive metalmaterial of the second layer is removed, with the insulating material ofthe first layer in the strip 10 being left intact. Upon the completionof such modified second saw cut S2, the solder bumps 56 are applied tothe leads 20 of the lead frame 12. Thereafter, a third saw cut iscompleted along essentially the same path as the second saw cut S2, withthe saw blade cutting only through the first layer due to the removal ofthe second layer as a result of the second cut saw S2. The blade used tocomplete the third saw cut will typically be slightly thinner than theblade used to complete the second saw cut S2.

The leads 20 of the lead frames 12 may each be provided with the solderbump 56 without necessarily completing the saw singulation of the stripin the aforementioned two-step or three-step process. In this regard,the solder bumps 56 could simply be formed on each of the leads 20, withthe cuts being completed in the manners previously described in relationto the first and second embodiments of the present invention. However,if the solder bumps 56 are to be formed on the leads 20 prior to thesingle cut (in the case of the first embodiment) or the two-step cut (inthe case of the second embodiment), such solder bumps 56 must becarefully positioned on the leads 20 so that the saw singulation processdoes not cause excessive burring or smearing thereof.

The solder bumps 56 are typically created by screen printing solderpaste on the leads 20, and are optimized for reworkability and secondlevel reliability. In current chip package designs, solderable surfacesare provided by the bottom surfaces of the leads as indicated above,with the chip package being attached to the printed circuit board byprinting solder paste on the board and completing a hot reflow process.Thus, the solder joint standoff height is completely dependent upon theamount of paste printed on the printed circuit board. The solder bumps56, if included on the leads 20, increase the standoff by two or threemils, thus enhancing solder joint reliability. Additionally, the reworkprocess at the printed circuit board level involves removing the oldcomponent, printing paste on the printed circuit board at the componentsite, and attaching a new component. For tight spaces, it is verydifficult to print paste on the printed circuit board, with the jointformation usually being relied upon by solder balls on CSP packages.This poses a challenge for MLF packages as there are no solder balls onthe package. By creating solder bumps 56 on the semiconductor package40, the same will not require solder paste printing on the printedcircuit board for reworking.

The portion of the semiconductor package 40 shown in FIG. 11 representswhat is typically referred to as a conventional “full lead design”. Asis evident from the aforementioned description of the semiconductorpackage 40, in the full lead design, at least portions of the bottomsurfaces 28 of the leads 20 are exposed within the bottom surface 46 ofthe package body 42, with the outer ends 32 of the leads 20 beingexposed within the side surface 50 of the package body 42. This fulllead design provides optimal solder joint reliability due to the largesolder fillet formed at the outer ends 32 of the leads 20. These solderfillets are enhanced by the inclusion of the recesses 34 within theouter ends 32 of the leads 20. However, the full lead design stillcarries a saw efficiency penalty attributable to the need to pass thesaw blade through the metal material within each saw street S and thesusceptibility of creating burrs at the outer ends 32 of the leads 20 asa result of the saw singulation process which are outside of anacceptable size range.

Referring now to FIG. 15, there is shown a semiconductor package 58which has an “inboard lead design” as an alternative to the full leaddesign of the semiconductor package 40. In the inboard lead design, thesemiconductor package 58 includes leads 60, each of which includes abottom surface 62. The bottom surface 62 of each lead 60 is exposedwithin the bottom surface 64 of the package body 66 of the semiconductorpackage 58, but is pulled back away from the side surface 68 of thepackage body 66. The exposed bottom surfaces 62 of the leads 60 definecontact points for solder paste used to form solder joints used toelectrically connect the leads 60 and hence the semiconductor package 58to an underlying substrate such as a printed circuit board. The inboardlead design of the semiconductor package 58 optimizes saw singulationefficiency due to the substantially decreased amount of metal which mustbe removed during the saw singulation process. However, due to thebottom surfaces 62 of the leads 60 being substantially flush with thebottom surface 64 of the package body 66, the solder joint reliabilitybetween the semiconductor package 58 and an underlying substrate isinferior to that typically achieved between a semiconductor packagehaving a full lead design and an underlying substrate.

The semiconductor package 58 of the inboard lead design as shown in FIG.15 includes certain enhancements to a typical inboard lead design whichare adapted to facilitate a substantial increase in solder jointreliability as compared to the typical inboard lead design. Moreparticularly, as shown in FIG. 15, the exposed bottom surface 62 of eachlead 60 has a bump 70 plated thereon. The bump 70 is preferably formedof copper. The application of the copper bump 70 to the bottom surface62 of each lead 60 preferably occurs upon the completion of theformation of the package body 66 via a molding process. Each copper bump70 may include a solder plate 84 formed thereon. The copper bump 70provides an increased solderable area that provides a desired solderfillet increasing the second level reliability of the solder jointsbetween the semiconductor package 58 and the underlying substrate suchas the printed circuit board 72 shown in FIG. 15. As shown in FIG. 15,the solder paste 74 used to form the solder joints between thesemiconductor package 58 and the printed circuit board 72 is able toflow up the sides of the copper bump 70 so as to provide theaforementioned increase in second level reliability. Thus, the modifiedinboard design of the semiconductor package 58 attributable to theinclusion of the copper bumps 70 upon the bottom surfaces 62 of theleads 60 provides the attributes of good solder joint reliabilitycoupled with greater efficiency in the saw singulation process.

Referring now to FIGS. 16A–F, there is shown a sequence of steps used tofacilitate the fabrication of semiconductor packages 58 having themodified inboard design described above. In the initial stage of thefabrication process, a metallic lead frame strip 76 defining multiplelead frames 78 has a tape layer 80 applied to one side thereof (FIG.16A). Thereafter, a mold cap 82 is formed upon the lead frames 78 (FIG.16B). Those surfaces of the leads and die pad of each lead frame 78 ofthe lead frame strip 76 which are covered by the tape layer 80 are notcovered by the mold cap 82.

Subsequent to the formation of the mold cap 82, the tape layer 80 isremoved from the lead frame strip 76 (FIG. 16C). Thereafter, theabove-described copper bump 70 is formed on the exposed bottom surfaceof each of the leads of each of the lead frames 78 (FIG. 16D). As shownin FIG. 16D, copper bumps 70 are also formed on the bottom surfaces ofthe die pads of the lead frames 78 which are also exposed within themold cap 82. After the copper bumps 70 have been formed, a solder plate84 is formed on each of the copper bumps 70 (FIG. 16E). Subsequent tothe formation of the solder plates 84, the lead frame strip 76 and moldcap 82 are subjected to a saw singulation process along the saw streetsdefined thereby so as to separate the individual semiconductor packages58 from each other (FIG. 16F). Each of the resultant semiconductorpackages 58 has the structural attributes described above in relation toFIG. 15.

This disclosure provides exemplary embodiments of the present invention.The scope of the present invention is not limited by these exemplaryembodiments. Numerous variations, whether explicitly provided for by thespecification or implied by the specification, such as variations instructure, dimension, type of material and manufacturing process may beimplemented by one of skill in the art in view of this disclosure.

1. A semiconductor package comprising: a die pad defining a bottomsurface; a plurality of leads extending at least partially about the diepad in spaced relation thereto, each of the leads defining: opposed topand bottom surfaces; and an outer end; a semiconductor chip attached tothe die pad and electrically connected to at least one of the leads; apackage body defining a generally planar bottom surface and partiallyencapsulating the die pad, the leads and the semiconductor chip suchthat at least a portion of the bottom surface of each of the leads isexposed in and substantially flush with the bottom surface of thepackage body; and means formed on the exposed portion of the bottomsurface of each of the leads for increasing a stand-off height of thesemiconductor package from an underlying substrate and providing anincreased solderable area to create a solder fillet when solder is usedto attach the semiconductor package to the substrate, the stand-offmeans being formed of a conductive material having a melting pointhigher than that of solder; and a solder plate disposed on the stand-offmeans.
 2. The semiconductor package of claim 1 wherein the stand-offmeans is further formed on the bottom surface of the die pad.
 3. Thesemiconductor package of claim 2 wherein the stand-off means comprises abump formed on the exposed portion of the bottom surface of each of theleads and the bottom surface of the die pad.
 4. The semiconductorpackage of claim 3 wherein the bump comprises copper.
 5. Thesemiconductor package of claim 3 wherein the bump is formed by a platingprocess.
 6. The semiconductor package of claim 1 wherein the bottomsurface of the die pad is exposed in and substantially flush with thebottom surface of the package body.
 7. The semiconductor package ofclaim 6 wherein: the package body defines multiple generally planar sidesurfaces; the outer end of each of the leads is exposed in andsubstantially flush with a respective one of the side surfaces.
 8. Asemiconductor package comprising: a die pad defining a bottom surface; aplurality of leads extending at least partially about the die pad inspaced relation thereto, each of the leads defining: opposed top andbottom surfaces; and an outer end; a semiconductor chip attached to thedie pad and electrically connected to at least one of the leads; apackage body defining a generally planar bottom surface and partiallyencapsulating the die pad, the leads and the semiconductor chip suchthat the at least a portion of the bottom surface of each of the leadsis exposed in and substantially flush with the bottom surface of thepackage body; a bump disposed on the exposed portion of the bottomsurface of each of the leads, the bump being formed of a conductivematerial having a melting point higher than that of solder, and beingsized and configured to increase a stand-off height of the semiconductorpackage from an underlying substrate and to provide an increasedsolderable area to create a solder fillet when solder is used to attachthe semiconductor package to the substrate; and a solder plate disposedon the bump.
 9. The semiconductor package of claim 8 wherein a bumpformed of a conductive material having a melting point higher than thatof solder is further disposed on the bottom surface of the die pad andincludes a solder plate disposed thereon.
 10. The semiconductor packageof claim 9 wherein the bump comprises copper.
 11. The semiconductorpackage of claim 9 wherein the bump is formed by a plating process. 12.The semiconductor package of claim 8 wherein the bottom surface of thedie pad is exposed in and substantially flush with the bottom surface ofthe package body.
 13. The semiconductor package of claim 12 wherein: thepackage body defines multiple generally planar side surfaces; the outerend of each of the leads is exposed in and substantially flush with arespective one of the side surfaces.
 14. In a semiconductor packagecomprising a die pad defining a bottom surface, a plurality of leadswhich each define a bottom surface and extend at least partially aboutthe die pad in spaced relation thereto, a semiconductor chip attached tothe die pad and electrically connected to at least one of the leads, anda package body defining a generally planar bottom surface and at leastpartially encapsulating the die pad, the leads, and the semiconductorchip such that the bottom surface of each of the leads is exposed in andsubstantially flush with the bottom surface of the package body, theimprovement comprising: means formed on the bottom surface of each ofthe leads for increasing a stand-off height of the semiconductor packagefrom an underlying substrate and providing an increased solderable areato create a solder fillet when solder is used to attach thesemiconductor package to the substrate, the stand-off means being formedof a conductive material having a melting point higher than that ofsolder.
 15. The semiconductor package of claim 14 wherein the stand-offmeans is further formed on the bottom surface of the die pad.
 16. Thesemiconductor package of claim 15 wherein the stand-off means comprisesa bump formed on the bottom surface of each of the leads and the bottomsurface of the die pad.
 17. The semiconductor package of claim 16wherein the bump comprises copper.
 18. The semiconductor package ofclaim 14 wherein the bump is formed by a plating process.
 19. Thesemiconductor package of claim 14 wherein the bottom surface of the diepad is exposed in and substantially flush with the bottom surface of thepackage body.
 20. The semiconductor package of claim 19 wherein: thepackage body defines multiple side surfaces; and each of the leadsdefines an outer end which is exposed in and substantially flush with arespective one of the side surfaces.